With the increase of the integration level of semiconductor devices, electrical insulation between metal lines such as bit lines and/or between metal lines and semiconductor layers may significantly affect the performance and reliability of a semiconductor device. As the integration level of semiconductor devices has increased, it has become more difficult to provide a sufficient process margin when forming a contact pad that is used to connect a transistor to a metal line such as a bit line or to a capacitor. Therefore, a process for forming a self-aligned contact (SAC) pad that is self-aligned to a metal line such as a gate line has been researched.
In the SAC pad forming process, when an opening for the contact pad is formed through an insulation layer, a capping layer and spacer of the metal line are used to self-align the opening on the metal line by suppressing etching. As such, a photoresist mask that has opening regions that are larger than the desired openings can be used as an etching mask while still obtaining sufficient process margin for the photolithography process.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor device having a contact plug.
Referring to FIG. 1, a gate structure (not shown) including a gate insulation layer, a gate electrode, a capping layer, and a spacer is formed on a semiconductor substrate 10 in which an isolation layer 11 and active regions such as source and drain regions 12 and 14 are defined. It will be appreciated that the semiconductor substrate may be a conventional semiconductor substrate, a semiconductor on insulator substrate, or an epitaxial or other semiconductor layer on a substrate. The gate structure is insulated from other metal lines by a first interlayer insulation layer 16. The first interlayer insulation layer 16 is etched to form openings exposing the active regions 12 and 14 in order to connect the active regions 12 and 14 to a bit line or a capacitor. The capping layer and the spacer in the gate structure may be used as an etching mask. Next, a conductive material such as polysilicon is deposited in the openings to form first and second contact plugs 20 and 30. The first contact plug 20 may comprise a storage contact plug (or a buried contact (BC)) that is electrically connected to the capacitor 40. The second contact plug 30 may comprise a bit line contact plug (or a direct contact (DC)) that is connected to the bit line. The first and second contact plugs 20 and 30 may be formed simultaneously.
The bit line contact plug that is connected to the bit line may include a barrier layer 32 to lower a potential barrier of contacts. The barrier layer 32 may be a single layer, for example, a titanium (Ti) layer or a multi-layer structure such as, for example, a titanium/titanium-nitride (Ti/TiN) layer. The barrier layer 32 may further include a metal layer such as a tungsten (W) layer. The metal layer is generally formed on the layer having titanium. When the barrier layer 32 has titanium, since titanium is highly reactive with silicon, the titanium in the barrier layer 32 naturally reacts with polysilicon in the second contact plug 30 to form a titanium silicide layer 32a at the interface between the second contact plug 30 and the barrier layer 32.
A capping layer 34 is formed on the barrier layer 32 and a spacer 36 is formed on side portions of the barrier layer 32. The capping layer 34 and the spacer 36 protect the barrier layer 32 during subsequent processing steps. The barrier layer 32 is connected to the bit line, and thus the active region (i.e., the source region) 14 is electrically connected to the bit line. Next, an insulation layer 38 that covers the bit line structure including the barrier layer 32 is formed.
The insulation layer 38 is etched to form openings in order to form a storage contact plug 22 that electrically connects the active region (i.e., the drain region) 12 to a capacitor 40. The capping layer 34 and the spacer 36 may be used as an etching mask. However, the spacer 36 may also be etched by the etchant, and thus the spacer 36 may have a profile shown by a dotted line 36a after this etching process is performed. When the spacer 36 is excessively etched, the silicide layer 32a may be exposed to the etchant. Since the etchant may contain, for example, hydrofluoric acid, the exposed silicide layer 32a may be undesirably decomposed by the etchant. As a result, the electrical contact of the active region 14 with the bit line may be deteriorated and thus a current may leak.